(1) Field of the Invention
The present invention relates generally to the field of logic synthesis for integrated circuit devices. More particularly, aspects of the present invention relate to methods and apparatus for design for test within a logic synthesis system.
(2) Background of the Related Art
Complex integrated circuits are designed with the use of computer aided design (CAD) tools. Specifically, application specific integrated circuits (ASICs) and field programmable gate array (FPGA) circuits can be designed using a variety of CAD tools. The development of ASICs and FPGA circuits with the aid of CAD tools is referred to as electronic design automatic or EDA. Design, checking and testing of large scale integrated circuits are so complex that the use of programmed computer systems are required for realization of normal circuits. This is partly because the integrated devices are inherently complex and partly because the circuit design needs to be decomposed into simpler functions which are recognized by the CAD tool. It is also partly because considerable computation is required in order to achieve an efficient layout of the resultant network. The result of the computerized design process is a detailed specification defining a complex integrated circuit in terms of a particular technology. This specification can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Integrated circuit designs can be represented in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. Two exemplary forms of HDL are Verilog and VHDL. The integrated circuit can be represented by different layers of abstractions (e.g., behavioral levels, structural levels and gate levels). An RTL level is an intermediary level of abstraction between the behavioral and structural levels. HDL descriptions can represent designs of all these levels.
The behavior levels and RTL levels consist generally of descriptions of the circuit expressed with program-like constructs, such as variables, operators conditional loops, procedures and functions. At the logic level, the descriptions of the circuit are expressed with Boolean equations. The HDL can be used along with a set of circuit constraints as an input to a computer implemented compiler (also called a xe2x80x9csilicon compilerxe2x80x9d). The computer implemented compiler program processes this description of the integrated circuit and generates therefrom a detailed list of logic components and the interconnections between these components. This list is called a xe2x80x9cnetlist.xe2x80x9d The components of a netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches and D-flip flops, etc. and their interconnections used to form a custom design.
In processing the HDL input, the compiler first generates a netlist of generic primitive cells that are technology independent. The compiler then applies a particular cell library to this generic netlist (this process is called mapping) in order to generate a technology dependent mapped netlist. The mapping process converts the logical representation which is independent of technology into a form which is technology dependent. The mapped netlist has recourse to standard circuits, or cells which are available within a cell library forming a part of the data available to the computer system.
Compiler programs and mapping programs are well known in the art and several of these systems are described in U.S. Pat. No. 5,406,497, by Altheimer et al.
An important part of the logic synthesis process involves designing for testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. As part of DFT, it is known to take the mapped netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. The act of applying test vectors is called stimulation of the design and the special memory cells and associated circuitry are referred to as DFT implementations. Issues concerning controllability deal with facilitating the application of the test vectors to the circuitry to be tested. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present.
The portions of an integrated circuit that are designed to perform its intended or expected operational function are called its xe2x80x9cmission modexe2x80x9d circuitry while the portions added to the integrated circuit to facilitate testability are called xe2x80x9ctest modexe2x80x9d circuitry or DFT implementations. The resultant circuit therefore has two functional modes, mission and test.
An exemplary flow chart diagram of a typical logic synthesis process, including a DFT process, is shown in FIG. 1. The processes 200 described with respect to this flow chart is implemented within a computer system in a CAD environment. High level design language (HDL) descriptions of the integrated circuit enter at block 201. Also accompanying the HDL 201 is a set of performance constraints 205 applicable to the design which typically include timing, area, power consumption, and other performance related limitations that the compiler 225 will attempt to satisfy when synthesizing the integrated circuit design. Constraints 205 can also include non-performance related constraints such as structural and routing constraints. Compiler 225 consists of a generic compiler 203 (also called an HDL compiler, RTL synthesizer, or architectural optimizer) that inputs the HDL 201 description and generates therefrom a technology independent or xe2x80x9cgenericxe2x80x9d netlist 207 which is also dependent on the constraints 205. As discussed above, the netlist 207 is a list of technology independent components or operators and the interconnections between them.
The generic netlist 207 is then input to a design compiler 209 that includes a computer implemented logic optimization procedure and a mapping procedure which interfaces with a technology dependent cell library 230 (e.g., from LSI, VLSI, TI or Xilinx technologies, etc.). The cell library 230 contains specific information regarding the cells of the specific technology selected such as the cell logic, number of gates, area consumption, power consumption, pin descriptions, etc., for each cell in the library 230. Logic optimization procedure of block 209 includes structuring and flattening procedures. The mapping procedure of block 209 generates a gate level mapped netlist 211 that is technology dependent having cells specifically selected to satisfy the constraints 205. This gate level netlist 211 consists at this point of xe2x80x9cmission modexe2x80x9d circuitry.
At block 212 of FIG. 1, DFT process 213 performs a particular test insertion process (here a scan) to implement testability cells or xe2x80x9ctest modexe2x80x9d cells into the overall integrated circuit design. In this process 213, memory cells of the mapped netlist 211 are replaced with memory cells that are specially designed to apply and observe test vectors or patterns to and from portions of the integrated circuit. In one particular DFT process, these memory cells specially designed for test are called scannable memory cells. The test vector patterns can be derived from combinational or sequential automatic test pattern generation (ATPG) processes depending on whether or not a full or partial scan is performed by the scan insertion process 213. Process 213 also performs linking groups of scannable memory cells into scan chains so that the test vectors can be cycled into and out of the integrated circuit design. The output of the scan insertion process 213 is a scannable netlist 215 that contains both mission and test mode circuitry.
A problem occurs in the prior art process of FIG. 1 in that the scan insertion process 213 does not take into account its impact on the mission mode design. Specifically, the addition of the testability cells (scannable cells), and interconnections there between (chaining resources), and the addition of other dedicated connections required for operation of the scan chains (e.g., scan clock routing and scan enable signal routing) can cause the overall design to violate one or more of the defined constraints 205.
Therefore, a second compile process 217 of FIG. 1 (full or incremental compile) is invoked by the prior art process 200 in order to more effectively optimize the scannable netlist 215 to the constraints 205. An incremental compile 217 does not process all existing structure as in a full compile, it only applies high level logical optimization to the unmapped portions of the design. Those unmapped portions are then mapped using a technology dependent library. During a process iteration, an incremental compile 217 always processes to decrease the circuit cost. However, although this second compile process 217 is only an incremental compile process, it applies mapping optimizations iteratively on the entire scannable netlist 215. As a result, processing time to perform the second compile process 217 can be on the order of weeks given conventional CAD technology and circuit complexity.
Alternatively, many prior systems utilize a full compile as the second compile process 217. The full compile process is similar to process 225 in that the full compile process at 217 applies mapping and logic optimizations to the entire design, not just the unmapped portions.
After the second compile process 217 of FIG. 1 completes, a scannable netlist 219 is again generated that contains the testability cells but that may or may not meet the original performance constraints 205. Therefore, at block 221, the prior art then performs a test to determine if the scannable netlist 219 meets the constraints 205. If the netlist 219 meets the constraints, then at block 235, other circuit synthesis procedures continue until the integrated circuit design can be fabricated onto a substrate and tested.
However, as is often the case, the addition of the testability cells by the scan insertion process 213 does not allow the second compile process 217 to meet constraints 205 without a design modification to the original HDL program 201. In such case, the overall process 200 flows from block 221 back to the HDL 201 where the architect modifies the HDL program 201 so that the addition of the testability cells and other resources will eventually satisfy, when possible, the given constraints 205 after the incremental compile step 217 is again executed.
The prior art process 200 of FIG. 1 has several disadvantages. It is disadvantageous to execute a second substantial compile process 217 in an attempt to match the testability cells and linking resources to the given set of constraints. Although this process can be an incremental compile step in that much of the gate level connections are not removed, mapping optimization portions of this compile process still operate in an iterative fashion over the entire design. The addition of this second compile process, using conventional technology, delays the overall integrated circuit synthesis process by as much as one to two weeks. Even after this long delay, there are no guarantees that the incremental compile process 217 will generate a scannable netlist satisfying the constraints 205. In this case, a time consuming task of returning to the HDL for redesign is required. This process involves the chip architect designers once more and, therefore, it is unclear under the prior art system when a designer can sign off on his or her work in the design process.
Another problem faced by prior art designs involving the introduction of scan cells for testability while maintaining optimization constraints (e.g., timing and area constraints) is that the timing and area constraints cannot be met in some designs if the entire design is scan replaced. This is true no matter how many conventional compile processes are executed after the scan insertion block. Therefore, it would be desirable to determine a set of sequential cells that can be scan replaced to just meet the timing and area constraints while offering significant testability for the design. What is needed is a system that effectively determines a set of sequential cells within a design that can be scan replaced while satisfying given timing and area constraints of the design. The present invention provides this functionality. Further, what is needed is a system that can perform the above based on iterations through determined critical paths of the design. The present invention additionally provides this functionality.
Accordingly, the present invention advantageously provides a system for effectively determining the amount of sequential cells within a design that can be scan replaced while satisfying given timing and area constraints of the design and still offering significant testability for the design. It is an object of the present invention to provide the above within a selected set of scan cells that attempts to offer a high degree of testability given the timing and area constraints to be satisfied. It is an object of the present invention to provide a subtractive system for performing the above wherein a fully scan replaced netlist (that violates timing and area constraints) is input and selected cells are unscanned until the timing and area constraints are met. It is another object of the present invention to provide an additive system wherein an unscanned netlist is received, and using a cell based or a critical path based system, cells are scanned that do not make the timing of the original system any worse than originally submitted until a significant number of sequential cells are scan replaced or area constraints are violated. These and other objects of the present invention not specifically recited above will become clear within discussion of the present invention herein.
A computer implemented process and system are described for effectively determining a set of sequential cells within a integrated circuit design that can be scan replaced (e.g. for design for test applications) to offer significant testability while still maintaining specified timing and area constraints that are applicable to the design. The novel system selects sequential cells of the set for scan replacement that offer best testability contribution while not selecting sequential cells for scan replacement that do not offer much testability contribution and/or are part of most critical paths within the design.
The novel system is composed of a subtractive method and an additive method that individually operate on different netlist types. The subtractive method inputs a fully scan replaced netlist (e.g., the sequential cells are call scan replaced) that does not meet determined optimization (e.g., area and/or timing) constraints. The subtractive process of the present invention can receive input, for example, from the output of a test ready compiler (TR) also of the present invention. The novel subtractive system unscans selected scannable cells until the timing constraints are met if a timing critical flag is set by the user. Additional cells are unscanned if area constraints are violated. Selection for unscanning is based on a testability cell list (TCL) that ranks cells by their degree of testability contribution; those cells with low degrees of testability are unscanned first. The additive process of the present invention receives an unscanned netlist (the xe2x80x9coriginal designxe2x80x9d) and scan replaces cells using the TCL until area constraints are violated or, if a timing-critical flag is set, until the performance of the design having the scan replaced cells are worse than the original design. An unscanned netlist for the additive process can be output from an conventional compiler or can be an imported netlist. The additive system iterates through the TCL list with the cells offering the most contribution for testability scan replaced first. Cells on critical paths, or subcritical paths that become critical when the cells are replaced, are not replaced if the user has asserted a timing-critical flag.
The present invention also includes a computer implemented process and system for electronic design automation (EDA) using groups of multiple cells having loop-back connections for modeling port electrical characteristics. Multi-bit cells have multiple gates of the same function implemented within a same cell. Multi-bit components have multiple multi-bit cells implemented within a same component. Scannable multi-bit cells and components are similar to multi-bit cells and components but contain scannable sequential elements with scan chains installed. Multi-bit cells may or may not have each sequential cells"" input and each sequential cells"" output available externally. The scannable sequential elements of a multi-bit component are ordered into a predefined scan chain which is defined by the library containing the multi-bit component or multi-bit cell. During scan replacement processes of the EDA compile process, multi-bit cells and components of the netlist are replaced with scannable multi-bit cells and components. Also, during optimization, multi-bit cells and components undergo equivalence replacement to meet specified constraints (e.g., area, performance, etc.). To model the electrical characteristics of the port during certain optimizations, loopback connections are applied to the multi-bit components from the scan out port to the scan in port of the multi-bit cell or component, therefore, one loopback connection spans multiple sequential cells within the multi-bit cell or component. During certain optimizations, loopback connections are applied to multiple sequential cells that are coupled together but do not necessarily reside in a multi-bit cell or component. By spanning multiple sequential cells, circuit degeneration is reduced thereby providing better circuit optimizations for netlists having scan circuitry.
Specifically, embodiments of the present invention include, in a computer system having a processor coupled to a bus and a memory coupled to the bus, a computer implemented subtractive method of generating a netlist having scannable sequential cells and satisfying determined optimization constraints (e.g., timing and area constraints), the method comprising the computer implemented steps of: receiving a ranked list ordering sequential cells by their contribution to testability; receiving a fully scan replaced input netlist including scannable sequential cells, the input netlist not satisfying one of the determined optimization constraints (e.g., area and/or timing); if timing constraints are violated and the user has asserted a timing-critical flag, determining a set of critical paths within the input netlist by performing a timing analysis on the input netlist and selecting a selected critical path of the set of critical paths and identifying a first and a second sequential cell located on either end of the selected critical path and if both sequential cells are scannable, determining, using the ranked list, which sequential cell of the selected critical path contributes least to testability and unscanning that sequential cell; repeating the above while critical paths with scannable sequential cells exist within the set of critical paths; and provided area constraints are violated, continue unscanning scannable cells that contribute least to testability until either area constraints are met or until there are no more scannable cells in the netlist.
Embodiments further include the above and wherein if only one sequential cell of the first and second sequential cells is scan replaced, unscanning it regardless of the ranked list. Embodiments further include the above and wherein the input netlist includes a loopback connection associated with each scannable sequential cell. Embodiments of the present invention include the above and wherein the ranked list comprises a list of sequential cells, each sequential cell having a rank number identifying its relative contribution to testability, and wherein sequential cells are determined to contribute least to testability by their rank number within the ranked list. The present invention also includes a computer system implemented in accordance with the above.
Embodiments of the present invention also include, in a computer system, an additive method of generating a netlist having scannable sequential cells and satisfying determined optimization constraints (e.g., timing and area constraints), the method comprising the computer implemented steps of: (a) accessing a ranked list ordering sequential cells by their contribution to testability; (b) accessing an unscanned input netlist including unscanned sequential cells; (c) selecting a selected unscanned sequential cell from the ranked list starting from an end of the ranked list that identifies sequential cells having high contributions to testability; (d) scanning the selected unscanned sequential cell, provided the step of scanning does not worsen timing characteristics or violate timing constraints of the input netlist, wherein the step (d) further comprises the steps of: (1) copying the input netlist to generate an input netlist copy; (2) scanning the selected unscanned sequential cell within the input netlist copy; (4) determining the worst critical path of the copy of the input netlist; (5) summing the areas of each logic and routing element of the input netlist copy to determine an area of the input netlist copy; (6) scanning the selected unscanned sequential cell within the input netlist provided the worst critical path of the input netlist copy is not worse than the worse critical path of the input netlist and provided the area of the input netlist copy does not violate the area constraints; (e) selecting a next selected unscanned sequential cell from the ranked list; and (f) repeating steps (d)-(e) for each unscanned sequential cell within the ranked list. The present invention also includes a computer system implemented in accordance with the above.
Embodiments of the present invention also include a method, in an electronic design automation system, of generating a netlist description comprising the computer implemented steps of: a) accessing an HDL specification representing an integrated circuit to be realized in physical form and accessing constraints applicable to the design; b) compiling the HDL specification with a compiler to produce a netlist description of the integrated circuit wherein the netlist description comprises multi-bit cells, multi-bit components and combinational logic, the step b) comprising the steps of: b1) inserting scannable multi-bit cells and scannable multi-bit components by replacing the multi-bit cells and the multi-bit components with equivalent scannable multi-bit cells and equivalent scannable multi-bit components, respectively; and b2) installing a loopback connection between a scan-out port of a respective scannable multi-bit cell and a scan-in port of the respective scannable multi-bit cell; and b3) installing a loopback connection between a scan-out port of a respective scannable multi-bit component and a scan-in port of the respective scannable multi-bit component; and c) storing the netlist description into computer memory.
Embodiments also include the above and wherein the step b) further includes the step of b4) optimizing the scannable multi-bit cells and the scannable multi-bit components according to the constraints by utilizing the loopback connections installed by steps b2) and b3) to simulate electrical characteristics of scan-in and scan-out ports of the scannable multi-bit cells and the scannable multi-bit components and wherein the step b4) comprises the steps of: installing a long loopback connection over multiple scan cells wherein the long loopback connection is coupled to a scan-in port of a first scan cell of the multiple scan cells and also coupled to a scan-out port of a last scan cell of the multiple scan cells; optimizing using the long loopback connection which prevents circuitry degeneration of the first and last scan cells; and removing the long loopback connection.